Memory device with non-volatile reference memory cell trimming capabilities

ABSTRACT

A non-volatile memory device comprising a primary memory array, at least one non-volatile reference memory cell and sense circuitry. The primary memory array has a plurality of memory cells. The sense circuitry is used to monitor the logic state of the memory cells. In addition, the memory device has an input connection to couple an external reference current to the sense circuitry to be used during the programming of the reference memory cell.

RELATED APPLICATION

[0001] This is a divisional application of U.S. patent application Ser.No. 09/818,957 filed Mar. 27, 2001, titled “Method and Apparatus ForTrimming Non-Volatile Memory Cells” and commonly assigned, the entirecontents of which is incorporated herein by reference.

TECHNICAL FIELD OF THE INVENTION

[0002] The present invention relates generally to non-volatile memoriesand in particular the present invention relates to trimming non-volatilereference memory cells.

BACKGROUND OF THE INVENTION

[0003] Memory devices are typically provided as internal storage areasin the computer. There are several different types of memory. One typeof memory is random access memory (RAM) that is typically used as mainmemory in a computer environment. Most RAM is volatile, which means thatit requires a steady flow of electricity to maintain its contents.Computers often contain a small amount of read-only memory (ROM) thatholds instructions for starting up the computer. An EEPROM (electricallyerasable programmable read-only memory) is a special type non-volatileROM that can be erased by exposing it to an electrical charge. Likeother types of ROM, EEPROM is traditionally not as fast as RAM. EEPROMcomprise a large number of memory cells having electrically isolatedgates (floating gates). Data is stored in the memory cells in the formof charge on the floating gates. Charge is transported to or removedfrom the floating gates by programming and erase operations,respectively.

[0004] Yet another type of non-volatile memory is a Flash memory. AFlash memory is a type of EEPROM that can be erased and reprogrammed inblocks instead of one byte at a time. A typical Flash memory comprises amemory array that includes a large number of memory cells arranged in arow and column fashion. Each memory cell includes a floating gatefield-effect transistor capable of holding a charge. The cells areusually grouped into erasable blocks. Each of the memory cells can beelectrically programmed in a random basis by charging the floating gate.The charge can be removed from the floating gate by an erase operation.Thus, the data in a cell is determined by the presence or absence of thecharge in the floating gate.

[0005] To program a memory cell, a high positive voltage Vg is appliedto the control gate of the cell. In addition, a moderate positivevoltage is applied to the drain (Vd) and the source voltage (Vs) and thesubstrate voltage (Vsub) are at ground level. These conditions result inthe inducement of hot electron injection in the channel region near thedrain region of the memory cell. These high-energy electrons travelthrough the thin gate oxide towards the positive voltage present on thecontrol gate and collect on the floating gate. The electrons remain onthe floating gate and function to reduce the effective threshold voltageof the cell as compared to a cell that has not been programmed. Aprogrammed non-volatile memory cell is said to be at a logic level of“0”.

[0006] In flash memories, blocks of memory cells are erased in groups.This is achieved by putting a negative voltage on the word lines of anentire block and coupling the source connection of the entire block toVcc (power supply), or higher. This creates a field that removeselectrons from the floating gates of the memory elements. In an erasedstate, the memory cells can be activated using a lower control gatevoltage. An erased non-volatile memory cell is said to be at a logiclevel of “1”.

[0007] Non-volatile memory systems, including flash memory systems, usea variety of sense amplifiers to verify the state of memory cells in amemory array. Verification of a non-volatile memory cell is accomplishedby applying a potential to the control gate of the cell to be verifiedand then using a sense amplifier to compare a current generated by thecell with a known current from a reference cell. The reference cell is anon-volatile memory cell or bit that has a predefined charge that is setor trimmed by the manufacture of the memory to produce a specificreference current in response to a known gate voltage. The senseamplifier determines whether the memory cell to be verified draws moreor less current than the reference current. By doing this, the senseamplifier determines if the memory cell is in a programmed state or anerased state.

[0008] The reference cell or cells are pre-programmed by the memorymanufactures. The time needed to program these cells to a desiredvoltage threshold (Vt) can be significant. Moreover, the longer it takesto program the cells the less memory devices can be produced for sale.Therefore, the longer the period of time needed to program referencecells, the more the memory device costs to make.

[0009] For the reasons stated above, and for other reasons stated belowwhich will become apparent to those skilled in the art upon reading andunderstanding the present specification, there is a need in the art foran improved method of pre-programming reference cells.

SUMMARY OF THE INVENTION

[0010] The above-mentioned problems with non-volatile memory devices andother problems are addressed by the present invention and will beunderstood by reading and studying the following specification.

[0011] In one embodiment, a non-volatile memory device comprises aprimary memory array, at least one non-volatile reference memory celland sense circuitry. The primary memory array has a plurality of memorycells. The sense circuitry is used to monitor the logic state of thememory cells. In addition, the memory device has an input connection tocouple an external reference current to the sense circuitry to be usedduring the programming of the reference memory cell.

[0012] In another embodiment, a flash memory device is disclosed. Theflash memory device includes a primary array, one or more flash memorycells and a sense amplifier for each flash reference memory cell. Theprimary memory array has a plurality of memory cells. The one or moreflash reference memory cells are used to verify the logic state of theplurality of memory cells in the primary array. Each sense amplifier hasa first input that is adapted to receive a bitline current from anassociated flash reference memory cell during a trimming operation ofthe associated flash reference memory cell. Each sense amplifier has asecond input that is adapted to receive an external reference currentfrom an external program reference tester. Each sense amplifier furtherhas an output that is coupled to the external reference program tester,wherein the output of each sense amplifier is used by the externalprogram reference tester to verify the program status of an associatedflash memory cells during the trimming operation.

[0013] In yet another embodiment, a non-volatile memory device isdisclosed. The non-volatile memory device comprises a primary memoryarray of non-volatile memory cells, one or more non-volatile referencememory cells, control circuitry and a sense amplifier for eachnon-volatile reference memory cell. The one or more non-volatilereference memory cells are adapted to provide a voltage threshold (Vt)level that is used in determining the logic state of the non-volatilememory cells in the memory array. The control circuitry is used tocontrol memory operations of the memory array and one or morenon-volatile reference cells. The control circuitry is adapted toreceive external trimming commands from an external reference programtester, wherein in response to the external trimming commands thecontrol circuitry performs trimming operations on the one or morenon-volatile reference memory cells. Each sense amplifier has a firstinput that is adapted to receive a bitline current from an associatednon-volatile reference cell during a trimming operation. Each senseamplifier has a second input that is adapted to receive an externalreference current during a trimming operation. Each sense amplifierfurther has an output to output a logic level based on the comparison ofan associated bitline current with an associated reference currentduring a trimming operation.

BRIEF DESCRIPTION OF THE DRAWINGS

[0014]FIG. 1 is a flow chart illustrating the pre-programming of areference cell of the prior art.

[0015]FIG. 2 is a block diagram of a memory device of an embodiment ofthe present invention.

[0016]FIG. 3 is a flow chart illustrating the pre-programming of areference cell of one embodiment the present invention.

DETAILED DESCRIPTION OF THE INVENTION

[0017] In the following detailed description of the preferredembodiments, reference is made to the accompanying drawings, which forma part hereof, and in which is shown by way of illustration specificpreferred embodiments in which the inventions may be practiced. Theseembodiments are described in sufficient detail to enable those skilledin the art to practice the invention, and it is to be understood thatother embodiments may be utilized and that logical, mechanical andelectrical changes may be made without departing from the spirit andscope of the present invention. The following detailed description is,therefore, not to be taken in a limiting sense, and the scope of thepresent invention is defined only by the claims.

[0018] The present invention reduces the test time required to trimreference cells to a specific threshold voltage by shortening a verifystep with the use of internal sense amplifiers in a memory device. Tobetter understand the present invention, further background is firstprovided.

[0019] Referring to FIG. 1, a flow chart of a traditional method oftrimming a reference cell (200) is illustrated. A reference cell istrimmed by first erasing the reference cell below the desired Vt (202).A program pulse is then applied to the reference bit or cell (204) tostore charge on the cell. A bitline access mode is then applied to thereference cell. The bitline access mode is a test mode that places avoltage, i.e. 1 volt, on the drain of the reference cell (206) and avoltage on the control gate of the reference cell (208). A testerportable memory unit (pmu) is then used to measure the current andverify if a reference cell (210) has reached the desired Vt. If thetarget Vt has not been reached on the reference cell, another programpulse is applied to the reference cell (204). Once again, a voltage isthen applied to the drain of the reference cell (206) and to the controlgate of the reference cell (208). The tester pmu once again measures thecurrent and verifies if the reference cell (210) has reached the Vt.This process is repeated until it is verified that a sufficient chargehas been stored on the floating gate of the reference cell.

[0020] The time required to verify a reference cell with a tester pmutakes a long period of time relative to the time needed to program thereference cell. Activating the tester pmu, to measure the current of thereference cell, can take up to 100 ms. Moreover, it can take seconds tocomplete verification if repeated cycles of applying program pulses tothe reference cell and measuring for Vt is required. Although a testerpmu or reference program tester is used in the present invention, abitline access mode is not used to measure the current of the referencecell to verify VT, thus no test time is wasted on tester pmu activationfor each verify cycle.

[0021] Referring to FIG. 2, one embodiment of the present invention isillustrated. FIG. 2 is a simplified illustration of the relevantelements of the present invention. As shown, a reference program testeror external tester equipment 102 is coupled to a memory device 100 tosupply a reference current to an input of sense amplifier 108 in acircuit of sense amplifiers 110. The reference program tester 102 has aninput 134 that is coupled to the output of the sense amplifier 108 toverify an output signal of the sense amplifier 108. Although, FIG. 2illustrates the reference program tester 102 being directly coupled tothe output of the sense amplifier 108, it will be understood in the artthat other elements of a non-volatile memory device (i.e. I/O buffer, ordata lines) may be coupled between the test circuit and the output ofthe sense amplifier and that the present invention is not limited to adirect connection of the reference program tester 102 to the senseamplifier 108.

[0022] The reference program tester 102 further has a command output(s)132 that is coupled to control circuitry 118 of the memory device 100 toprovide external commands to the control circuitry 118. The controlcircuitry 118 controls erase, program and other memory operations of thememory device 100. A high voltage switch/pump 116 is also shown toprovide a voltage source for the program pulses applied to the memorycells. A reference cell or reference memory cell 106 is illustrated inthe memory array 104. A drain of the reference cell 106 is coupled toanother input of the sense amplifier 108 by a bitline 120. The memorydevice 100 is further shown as having a column decode circuit 112 and arow decode circuit 114. Although, FIG. 2 is shown as only having onereference cell, it will be understood in the art that a memory devicemay have more than one reference cell and that the present invention isnot limited to one reference cell. Further, the reference cells may belocated in a separate “mini” array and not located with the primary dataarray.

[0023] Referring to FIG. 3, a flow chart of a method of trimming areference cell (300) of the present invention is illustrated. Thereference cell 106 is first erased below a desired Vt (302) by thecontrol circuitry 118. A reference current output 130 of the referenceprogram tester 102 then supplies a reference current to an input ofsense amplifier 108. The reference current level is equal to a currentlevel that would be indicative of a current supplied by an accessedmemory cell having the desired Vt. The reference current is supplied tothe sense amplifier 108 during the remainder of the trimming cycle. Alow level program pulse is then applied to the control gate of thereference cell 106 (306) to gently charge up the reference cell 106. Thelow level program pulse is used to add a small charge to the referencecell. In one embodiment, the low level program pulse includes applyingapproximately 8 volts to the control gate of the reference cell andapproximately 5.4 volts to the drain of the reference cell while thesource and the substrate of the reference cell is at ground level. Thislow level program pulse is applied for a period of approximately 1 ms.The reference cell 106 is then read (308). As known to those in the art,a cell is read by providing a predetermined access voltage to a wordlinecoupled to a control gate of the cell. For, example, in one embodiment,an access voltage of approximately 3.9 volts is used. In anotherembodiment, an access voltage of approximately 3.4 volts is used. Inresponse to the access voltage, the cell provides a cell or bit currentin a bitline that is coupled to a drain of the cell. The cell or bitcurrent in the bitline is indicative of the charge stored on the cell orbit.

[0024] Reading or accessing the reference cell provides a cell currentfrom the reference cell 106 to the other input of the sense amplifier108. The sense amplifier 108 then compares the cell current supplied bythe reference cell 106 to the reference current supplied by thereference program tester 102 (310). The sense amplifier outputs a logiclevel of a “1” or a logic level of a “0”. In one embodiment of thepresent invention, an output of a logic level 1 indicates the referencecell is below the desired Vt and that an additional program pulse isneeded and an output of a logic level 0 indicates the reference cellexceeds the desired Vt. In this embodiment, when the output transitionsfrom a logic level 1 to a logic level 0, the trimming cycle is complete.In another embodiment of the present invention, an output of a logiclevel 0 indicates the reference cell is below the desired Vt and that anadditional program pulse is needed and an output of a logic level 1indicates the reference cell exceeds the desired Vt. In this embodiment,when the output transitions from a logic level 0 to a logic level 1, thetrimming cycle is complete. Verifying with the use of internal senseamplifiers of a memory device can be done in approximately 200 ns percycle. That is, it only takes about 200 ns to verify the state of areference cell after a program pulse has been applied.

[0025] Unlike the prior art method of verifying a reference cell, thepresent invention does not directly measure the reference current butmonitors the logic output of the memory device containing the referencecell. That is, the present invention verifies a reference cell when thereference cell transitions from a memory cell having a voltage levelbelow the desired Vt to a memory cell having a voltage level above thedesired Vt as indicated by the logic output. The resulting voltage levelon the reference cell provides a current that is above the referencecurrent. The difference in the resulting voltage level on the referencecell is determined by the strength of the program pulse applied. Thatis, the lower the strength of the program pulse, the less charge will bestored on the floating gate of the memory cell and the closer thevoltage level of the reference memory cell will be to the desired Vtlevel once the logic output changes. A longer programming pulse willprogram the reference cell with less programming pulses, but shorterprogramming pulses provide for a more accurate trim.

CONCLUSION

[0026] A method and apparatus for trimming a non-volatile memory cellhas been disclosed. One method comprising, erasing the memory cell belowa desired voltage threshold (Vt) level, applying a program pulse to thememory cell, reading the memory cell, comparing a current conducted bythe memory cell with an externally provided reference current using asense amplifier that is internal to a memory device that contains thememory cell, producing a digital output based on the comparison of thecurrents and applying successive program pulses until the digital outputchanges from one logic state to another.

[0027] Although specific methods and embodiments have been illustratedand described herein, it will be appreciated by those of ordinary skillin the art that any arrangement, which is calculated to achieve the samepurpose, may be substituted for the specific embodiment shown. Thisapplication is intended to cover any adaptations or variations of thepresent invention. Therefore, it is manifestly intended that thisinvention be limited only by the claims and the equivalents thereof.

What is claimed is:
 1. A non-volatile memory device comprising: aprimary memory array having a plurality of memory cells; at least onenon-volatile reference memory cell; sense circuitry to monitor the logicstate of the memory cells; and wherein the memory device has an inputconnection to couple an external reference current to the sensecircuitry to be used during the programming of the at least onereference memory cell.
 2. The non-volatile memory device of claim 1wherein the at least one reference memory cell is located within theprimary memory array.
 3. The non-volatile memory device of claim 1wherein the at least one reference memory cell is a located in aseparate array of reference memory cells.
 4. The non-volatile memorydevice of claim 1 further comprising: control circuitry to controlmemory operations, wherein the control circuitry couples a predefinedvoltage to a control gate of the at least one reference memory cell tocreate a cell current for the sense circuitry to compare with theexternal reference current.
 5. The non-volatile memory device of claim 4wherein the control circuitry selectively provides program pulses to theat least one reference memory cell.
 6. A flash memory device comprising:a primary memory array having a plurality of memory cells; one or moreflash reference memory cells adapted to verify the logic state of theplurality of memory cells in the primary array; and a sense amplifierfor each flash reference memory cell, each sense amplifier having afirst input adapted to receive a bitline current from an associatedflash reference memory cell during a trimming operation of theassociated flash reference memory cell, each sense amplifier having asecond input adapted to receive an external reference current from anexternal program reference tester, each sense amplifier further havingan output coupled to the external reference program tester, wherein theoutput of each sense amplifier is used by the external program referencetester to verify the program status of an associated flash memory cellduring the trimming operation.
 7. The flash memory device of claim 6,wherein the one or more flash reference memory cells are located withinthe primary memory array.
 8. The flash memory device of claim 6, furthercomprising: a mini array of flash memory cells, wherein the one or moreflash reference memory cells are located within the mini array.
 9. Theflash memory device of claim 6, further comprising: control circuitry tocontrol operations of the flash memory device, the control circuitryadapted to receive external commands from the external reference programtester, wherein the external commands from the external referenceprogram tester direct the control circuitry to perform the trimmingoperations on the one or more flash reference memory cells.
 10. Theflash memory device of claim 9, wherein in response to the externalcommands the control circuitry erases the one or more flash referencememory cells, applies a program pulse to the one or more flash referencememory cells and performs a read operation on the one or more flashreference memory cells.
 11. The flash memory device of claim 10, furthercomprising: a high voltage switch/pump adapted to apply the programpulse to the one or more flash reference memory cells under control ofthe control circuitry.
 12. A non-volatile memory device comprising: aprimary memory array of non-volatile memory cells; one or morenon-volatile reference memory cells adapted to provide a voltagethreshold (Vt) level used in determining the logic state of thenon-volatile memory cells in the memory array; control circuitry tocontrol memory operations of the memory array and one or morenon-volatile reference cells, the control circuitry adapted to receiveexternal trimming commands from an external reference program tester,wherein in response to the external trimming commands the controlcircuitry performs trimming operations on the one or more non-volatilereference memory cells; and a sense amplifier for each non-volatilereference memory cell, each sense amplifier having a first input adaptedto receive a bitline current from an associated non-volatile referencecell during a trimming operation, each sense amplifier having a secondinput adapted to receive an external reference current during a trimmingoperation, each sense amplifier further having an output to output alogic level based on the comparison of an associated bitline currentwith an associated reference current during a trimming operation. 13.The non-volatile memory device of claim 12, wherein the second input ofeach sense amplifier is adapted to receive the external referencecurrent from the external reference program tester.
 14. The non-volatilememory device of claim 12, wherein the output of each sense amplifier isadapted to be coupled to the external reference program tester todetermine the logic level.
 15. The non-volatile memory device of claim12, wherein the reference current is approximately equivalent to acurrent output from a memory cell programmed to the Vt level during aread operation.
 16. The flash memory device of claim 12, wherein the oneor more non-volatile reference memory cells are located within theprimary memory array.
 17. The flash memory device of claim 12, furthercomprising: a mini array of flash memory cells, wherein the one or morenon-volatile reference memory cells are located within the mini array.18. The flash memory device of claim 12, wherein each non-volatilereference memory cell is properly trimmed when the logic level outputfrom an associated sense amplifier switches from a first logic level toa second logic level.
 19. The non-volatile memory device of claim 12,wherein the trimming operation includes erasing the one or morenon-volatile reference memory cells, providing one or more programpulses to the one or more non-volatile reference memory cells andreading the one or more non-volatile reference memory cells.
 20. Theflash memory device of claim 12, further comprising: a high voltageswitch/pump adapted to apply the one or more program pulses to the oneor more flash reference memory cells under control of the controlcircuitry.